1. Technical Field
The present invention relates to phase error cancellation in frequency dividers of the kind in which a division ratio is varied with time so that, over time, a desired average division ratio is obtained. The invention relates to phase-cancellation circuits per se, and to circuits, such as phase-locked loops, fractional dividers and frequency synthesizers, incorporating same.
2. Background Art
Known frequency dividers use different division ratios to obtain an average division ratio. Because each different division ratio produces a different phase delay, the phase difference between the input signal and the output or divided signal varies. Because the division ratios are known, the phase variation or error can be predicted, and means provided to compensate for it, or cancel it.
One compensation approach is to use a Delta-Sigma modulator to vary the division ratio more randomly. Thus, it is known for frequency synthesizers to use Delta-Sigma Modulators and integer-N dividers. A Delta-Sigma Modulator produces a quantized (1 to several bit) output from a high resolution (many bit and/or analog) input with the error resulting from this quantization spectrally shaped to reduce the spectral density of the error within some predetermined signal bandwidth. For frequency synthesizer applications, this bandwidth is typically centered around dc and multiples of the Delta-Sigma Clock frequency. Examples of such frequency synthesizers can be found in U.S. Pat. No. 4,965,531 (Riley) and U.S. Pat. No. 5,495,206 (Hietala) which are incorporated herein by reference. A disadvantage of these synthesizers is that the quantization step size is inherently 1 cycle of the high frequency signal, with frequency Fo and period To=1/Fo, applied to the divider. This makes the quantization noise large relative to the high frequency input signal.
Delta-Sigma modulators for use in frequency synthesizers may comprise other smaller Delta-Sigma modulator units. For example, in “Design and Realization of a Digital Delta-Sigma Modulator for Fractional-n Frequency Synthesis” by T. P. Kenny, T. A. D. Riley, N. M. Filiol and M. A. Copeland presented in the IEEE Transactions on Vehicular Technology, March 1999, many possibilities are disclosed. Many MASH type of Delta-Sigma modulators use a quantity which, for convenience, will be called herein the “Residual Quantization Error”, (R). In a Delta-Sigma modulator, there are many well known ways to obtain this Residual Quantization Error R. For example, the aforementioned paper illustrates and discusses a first order Delta-Sigma Modulator with single bit quantizer that is equivalent to an accumulator and in which the sum output represents the Residual Quantization error R. In this case the accumulator provides an Inherent Residual Quantization Error, R. This error is described as “inherent” because it is available for use with no added circuitry.
U.S. Pat. No. 5,055,802 (Heitala) discloses a Delta-Sigma modulator for use in a synthesizer in which the quantizer is a means for selecting the most significant bits (MSBs) of a digital signal to be quantized, the remaining least significant bits (LSBs) providing the Residual Quantization Error R. Since these LSBs are required to be there for the accumulator to function, they provide an Inherent Residual Quantization Error R. If this residual quantization error R is not available inherently, it can be derived explicitly by subtracting the output of the quantizer from the input to the quantizer. This difference then provides an Explicit-Difference Residual Quantization Error R.
Such Delta-Sigma modulator-based devices are not entirely satisfactory, however, because the minimum phase deviation which they can introduce is one full cycle of the high frequency signal applied to the divider. As a result, the error signals are relatively large and cause unacceptable jitter at the output of the divider.
The alternative approach uses a phase error cancellation circuit to subtract an error signal known a priori from the input signal before application to the divider or from the divided signal leaving the divider, or a signal derived therefrom. The circuit disclosed in U.S. Pat. No. 5,495,206 (Hietala), supra, not only modulates the division ratio directly but also provides partial cancellation of the phase error caused by the varying division ratio. Hietala's approach is not entirely satisfactory, however, because it does not reduce the jitter at the output of the divider, specifically because the minimum step size at the delta-sigma modulator output remains equal to 1 cycle of the high frequency input. Furthermore, Hietala does not disclose a fractional divider wherein the delta-sigma step size is less than one cycle of the high frequency input signal. In FIG. 5 of Hietala, a charge pump 153 subtracts an estimate of the error signal, known a priori, from a signal derived from the output of divider 140 by a phase detector 152. When the error signal is subtracted from a signal derived from the divider output, it is necessary to match the error signal path with the divider output path in both gain and delay. For this reason, it is preferred to cancel the error within the divider. This preference has been recognized in the prior art but does not detract from the general equivalence of subtracting the error within the divider and subtracting the error form a signal derived from the divider output.
In other known devices, a separate phase error cancellation circuit is provided, for example entirely within a fractional divider, or comprising some components inside and others outside the fractional divider. Generally, however, although these known phase error cancellation circuits provide correction smaller than one cycle of the high frequency divider input, they utilize an error-reduction signal which is periodic. As a result, the error-correction signal and hence the output or divided signal are subject to spurs, i.e., periodically-occurring phase errors.
A conventional divider will have a rising edge and a falling edge for each cycle of the divider output. Many phase detectors respond to only one of these two edges, the “active” edge, in which case the period of the divider is the time between two consecutive active edges. Fractional division can be achieved with a combination of counting input cycles at the divider input and delaying the active edge of the divider output. For example, dividing by 5¼ can be achieved by the following steps:    (i) counting 5 cycles and delaying the active edge by ¼ of a cycle;    (ii) counting a further 5 cycles and delaying the active edge by ½ of a cycle;    (iii) counting a further 5 cycles and delaying the active edge by ¾ of a cycle;    (iv) counting a further 6 cycles and not delaying the active edge.These steps then are repeated.
A Controlled Delay Divider may be used to perform these steps. A Controlled Delay Divider (CDD) produces an output pulse at a frequency (having a period and a controlled delay), FDIV, from one or more high frequency inputs having a frequency, Of. The period may be either predetermined, or controlled by an external input N, such that each period of the output pulse is N times the period of the input frequency plus some additional controlled delay. In a CDD, this delay can be controlled by a delay control input R which causes the additional delay to be R times dT, where dT is typically some predetermined fraction 1/Np, of high frequency input period. In the example above, Np is 4 and the ordered pair (N,R) takes on values (5,1), (5,2), (5,3), (6,0). The prior art has recognized that the sequence of values for R can be provided by a modulo Np accumulator with the carry out of the accumulator incrementing the integer part of the desired division ratio. It should be noted that the input signal N is the signal that causes the divider to divide by N and need not necessarily be a binary representation of the number N. For example, a divider that loads the binary number k and counts up from there to 255 and then reloads a new value for k, will divide by N=256−k.
Some divider architectures will have a more complicated input that causes the divider to divide by N. As another example, high speed dividers designed for low power consumption may have two binary words producing a composite input which causes the divider to divide by N; one of these words may be sent to an M-counter, the other word to an A-counter with the divide ratio N further depending on a predetermined prescaler value also. Although these relationships may be complicated, they are well defined in the prior art and within the skill of those versed in that art. Similarly, the delay control input, R, is the input which causes the delay to be R times dT regardless of how the signal R is represented or how the signal R controls the controlled delay. To further clarify the meaning and to illustrate the reduction to practice of a CDD, two examples are provided. U.S. Pat. No. 5,448,191 (Meyer), which is incorporated herein by reference, describes an Edge Selecting Controlled delay divider. In Meyer's device, the three phases of the high frequency divider input, Φ1, Φ2 and Φ3, are generated by a three-stage voltage-controlled ring oscillator (VCO) oscillating at a frequency Of. This allows the output of the divider to be delayed by 0, ⅓ or ⅔ of one VCO cycle. Ideally these three phases should have exactly 0, 120 and 240 degrees of phase shift, but mismatches in the stages of the ring oscillator or (more generally) unmatched delays through the divider may cause some Delay Error. Difficulties in maintaining an equal distribution of phase shift or (more generally) a linear and properly scaled relationship between the delay control input and the Controlled Delay have limited the applicability of this type of fractional divider. Techniques to improve the delay linearity have also been disclosed in the prior art.
An improved ring oscillator with individually calibrated delays is described in “A 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching”, Chan-Hong Park, et al., published in the IEEE Journal of solid state circuits May 2001, which is incorporated herein by reference. This example also illustrates how Controlled Delay is linearized through a feedback loop around each individual delay stage.
In both of these two Controlled Delay Divider examples, the different phases are generated outside the divider, but this is not generally necessary for a controlled Delay Divider.
These two examples also illustrate how Fractional Dividers comprising a Controlled Delay Divider can be used in a phase-locked loop (PLL) to create a fractional-N synthesizer. Limitations of such PLL synthesizers based on Controlled Delay Dividers are that they have resolution limited to the reference frequency divided by the number of available phases. If they are adapted to provide higher resolution by quantizing the accumulator value to use only the number of available phases, they produce “spurs”, i.e., spurious output tones. This occurs even in the absence of errors in the controlled delay of the different phases. As illustrated in the article by Chan-Hong Park, et al., these spurious tones may be produced even when these errors are individually compensated.
There remains a need, therefore, for a phase cancellation circuit which reduces phase errors caused by spurs without using large error signals.